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author | zbao <fishbaozi@gmail.com> | 2012-07-02 15:32:58 +0800 |
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committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-03 09:38:55 +0200 |
commit | 2c08f6ade4ac904e9eb762c71f95daa372be0072 (patch) | |
tree | 5ae613c6a0fe7285b6a5129fdc984953c462b801 /src/cpu/amd/agesa/family15tn/Kconfig | |
parent | 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc (diff) |
AGESA F15 wrapper for Trinity
The wrapper for Trinity. Support S3. Parme is a example board.
Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn/Kconfig')
-rw-r--r-- | src/cpu/amd/agesa/family15tn/Kconfig | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig new file mode 100644 index 0000000000..8f3a9ffb44 --- /dev/null +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -0,0 +1,79 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15_TN + bool + select PCI_IO_CFG_EXT + +config CPU_ADDR_BITS + int + default 36 + depends on CPU_AMD_AGESA_FAMILY15_TN + +config CPU_SOCKET_TYPE + hex + default 0x10 + depends on CPU_AMD_AGESA_FAMILY15_TN + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + depends on CPU_AMD_AGESA_FAMILY15_TN + +config EXT_RT_TBL_SUPPORT + bool + default n + depends on CPU_AMD_AGESA_FAMILY15_TN + +config EXT_CONF_SUPPORT + bool + default n + depends on CPU_AMD_AGESA_FAMILY15_TN + +config CBB + hex + default 0x0 + depends on CPU_AMD_AGESA_FAMILY15_TN + +config CDB + hex + default 0x18 + depends on CPU_AMD_AGESA_FAMILY15_TN + +config XIP_ROM_BASE + hex + default 0xfff80000 + depends on CPU_AMD_AGESA_FAMILY15_TN + +config XIP_ROM_SIZE + hex + default 0x100000 + depends on CPU_AMD_AGESA_FAMILY15_TN + +config HAVE_INIT_TIMER + bool + default y + depends on CPU_AMD_AGESA_FAMILY15_TN + +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0xA1000 + depends on CPU_AMD_AGESA_FAMILY15_TN |