diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-21 03:31:02 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-27 11:27:51 +0100 |
| commit | eaab6305beb587777248bf46a894050ed2a76b78 (patch) | |
| tree | 79de3d2d1e8eb82b432fcce7672b3f6cdea06a52 /src/cpu/amd/agesa/family15rl/Makefile.inc | |
| parent | 12bb8f97b6e453ea2cc99607efb443025271f3d8 (diff) | |
cpu/amd/agesa/family15rl: Provide Richland CPU support
Richland -
Microarchitecture: Piledriver
Core stepping: RL-A1
CPUID: 610F31
Change-Id: I790085fbf36d836c903dcce77d794abb8578712b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7537
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa/family15rl/Makefile.inc')
| -rw-r--r-- | src/cpu/amd/agesa/family15rl/Makefile.inc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc new file mode 100644 index 0000000000..a8f644d241 --- /dev/null +++ b/src/cpu/amd/agesa/family15rl/Makefile.inc @@ -0,0 +1,32 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chip_name.c +ramstage-y += model_15_init.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c + +subdirs-y += ../../mtrr +subdirs-y += ../../smm +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm |