AGESA f15 cimx/sb700: Remove unused chips code

Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

6 files changed, 0 insertions, 458 deletions

diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
deleted file mode 100644
index 94a38398ca..0000000000
--- a/src/cpu/amd/agesa/family15/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config CPU_AMD_AGESA_FAMILY15
-	bool
-	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY15
-
-config CPU_ADDR_BITS
-	int
-	default 48
-
-config CPU_AMD_SOCKET_G34
-	bool
-	default n
-	help
-	  AMD G34 Socket
-
-config CPU_AMD_SOCKET_C32
-	bool
-	default n
-	help
-	  AMD C32 Socket
-
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-
-config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
-	bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
-	default n
-	help
-	  This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
-
-	  Warning: Only enable this option when debuging or tracing AMD AGESA code.
-
-endif #CPU_AMD_AGESA_FAMILY15
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
deleted file mode 100644
index d01cb2aec5..0000000000
--- a/src/cpu/amd/agesa/family15/Makefile.inc
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
-
-romstage-y += fixme.c
-romstage-y += romstage.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_15_init.c
diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c
deleted file mode 100644
index f044e4069a..0000000000
--- a/src/cpu/amd/agesa/family15/chip_name.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_family15_ops = {
-	CHIP_NAME("AMD CPU Family 15h Model 00h-0Fh")
-};
diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c
deleted file mode 100644
index bf791b521f..0000000000
--- a/src/cpu/amd/agesa/family15/fixme.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
-#include "amdlib.h"
-
-UINT64
-MsrRead (
-	IN       UINT32 MsrAddress
-	);
-
-VOID
-MsrWrite (
-	IN       UINT32 MsrAddress,
-	IN       UINT64 Value
-	);
-
-
-UINT64
-MsrRead (
-	IN       UINT32 MsrAddress
-	)
-{
-	return __readmsr (MsrAddress);
-}
-
-VOID
-MsrWrite (
-	IN       UINT32 MsrAddress,
-	IN       UINT64 Value
-	)
-{
-	__writemsr (MsrAddress, Value);
-}
-
-void amd_initcpuio(void)
-{
-	UINT32			PciData;
-	PCI_ADDR		PciAddress;
-	AMD_CONFIG_PARAMS	StdHeader;
-	UINT32			nodes;
-	UINT32			node;
-	UINT32			sblink;
-	UINT32			i;
-	UINT32			TOM;
-
-	/* get the number of coherent nodes in the system */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
-	LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
-
-	/* Find out the Link ID of Node0 that connects to the
-	 * Southbridge (system IO hub). e.g. family10 MCM Processor,
-	 * sbLink is Processor0 Link2, internal Node0 Link3
-	 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
-	LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	sblink = (PciData >> 8) & 3; //assume ganged
-
-	/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
-	for (node = 0; node < nodes; node++) {
-		/* clear all MMIO Mapped Base/Limit Registers */
-		for (i = 0; i < 8; i++) {
-			PciData = 0x00000000;
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		}
-
-		/* clear all IO Space Base/Limit Registers */
-		for (i = 0; i < 4; i++) {
-			PciData = 0x00000000;
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		}
-
-		/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
-		PciData = 0x00000B00;
-		PciData |= sblink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
-		PciData = 0x00000A03;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set TOM1-FFFFFFFF to Node0 sbLink. */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
-		PciData = 0x00FFFF00;
-		PciData |= sblink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		TOM = (UINT32)MsrRead(TOP_MEM);
-		PciData = (TOM >> 8) | 0x03;
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set MMCONF space to Node0 sbLink with NP set.
-		 * default E0000000-EFFFFFFF
-		 * Just have all mmio set to non-posted,
-		 * coreboot not implemente the range by range setting yet.
-		 */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
-		PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
-		PciData = (PciData >> 8) & 0xFFFFFF00;
-		PciData |= 0x80; //NP
-		PciData |= sblink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
-		PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-
-		/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink  and enabled VGA IO*/
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
-		PciData = 0x00FFF000;
-		PciData |= sblink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
-		PciData = 0x00000033;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	}
-}
-
-void amd_initmmio(void)
-{
-	UINT64                        MsrReg;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/*
-	 * Set the MMIO Configuration Base Address and Bus Range onto
-	 * MMIO configuration base Address MSR register.
-	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
-	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
-}
-
-#if 0
-#include <cpuFamilyTranslation.h>
-
-void cpu_show_tsc(void)
-{
-	UINT32 TscRateInMhz;
-	CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-	GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
-				    &AmdParamStruct.StdHeader);
-	FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
-	printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
-}
-#endif
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
deleted file mode 100644
index 531bf29ae9..0000000000
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/pae.h>
-
-#include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
-
-static void model_15_init(device_t dev)
-{
-	printk(BIOS_DEBUG, "Model 15 Init.\n");
-
-	u8 i;
-	msr_t msr;
-	int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	u32 siblings;
-#endif
-
-	disable_cache ();
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	// BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs
-	msr.lo = msr.hi = 0;
-	wrmsr (0x259, msr);
-	msr.lo = msr.hi = 0x1e1e1e1e;
-	for (msrno = 0x268; msrno <= 0x26f; msrno++)
-		wrmsr (msrno, msr);
-
-	msr.lo = 0x04040404; msr.hi = 0x04040404;
-	wrmsr(0x259, msr);
-
-	/* disable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, msr);
-	enable_cache ();
-
-	/* zero the machine check error status registers */
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < 6; i++) {
-		wrmsr(MCI_STATUS + (i * 4), msr);
-	}
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
-	/* DisableCf8ExtCfg */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.hi &= ~(1 << (46 - 32));
-	wrmsr(NB_CFG_MSR, msr);
-
-
-	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_15_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x100F80},    /* HY-D0 */
-	{ X86_VENDOR_AMD, 0x100F90},    /* HY-D0 */
-	{ X86_VENDOR_AMD, 0x100F81},    /* HY-D1 */
-	{ X86_VENDOR_AMD, 0x100F91},    /* HY-D1 */
-	{ X86_VENDOR_AMD, 0x600f00 },   /* OR_A0x */
-	{ X86_VENDOR_AMD, 0x600f01 },   /* OR_A0x */
-	{ X86_VENDOR_AMD, 0x600f10 },   /* OR_B0x */
-	{ X86_VENDOR_AMD, 0x600f11 },   /* OR_B1x */
-	{ X86_VENDOR_AMD, 0x600f12 },   /* OR_B2x */
-	{ X86_VENDOR_AMD, 0x600f13 },   /* OR_B3x */
-	{ X86_VENDOR_AMD, 0x600f20 },   /* OR_C0x */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
deleted file mode 100644
index 46c03910f7..0000000000
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2017 Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <lib.h>
-#include <reset.h>
-
-#include <console/console.h>
-#include <cpu/amd/car.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-#include "northbridge/amd/agesa/family15/reset_test.h"
-#include <nb_cimx.h>
-#include <sb_cimx.h>
-
-void platform_once(struct sysinfo *cb)
-{
-	/*
-	 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
-	 * Disable all Pcie Bridges to work around It.
-	 */
-	sr56x0_rd890_disable_pcie_bridge();
-
-	nb_Poweron_Init();
-
-	sb_Poweron_Init();
-
-	board_BeforeAgesa(cb);
-}
-
-#if 0
-	/* Was between EARLY and POST */
-
-	nb_Ht_Init();
-	post_code(0x3D);
-	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		distinguish_cpu_resets(0);
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-#endif