diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-08-07 07:27:57 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-08 17:51:16 +0000 |
| commit | bd4a3f8cd9ec4c59ad1d33102958e525a9c8c6ef (patch) | |
| tree | f796856ba45aa571fdf4c936c4333ee6643c5db3 /src/cpu/amd/agesa/family14/model_14_init.c | |
| parent | e13dd172b12a51472641939c42005d40d7328836 (diff) | |
cpu/amd: Correct number of MCA banks cleared
Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear. The generations should have the following
number of banks:
* Family 10h: 6 banks
* Family 12h: 6
* Family 14h: 6
* Family 15h: 7
* Family 16h: 6
Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/amd/agesa/family14/model_14_init.c')
| -rw-r--r-- | src/cpu/amd/agesa/family14/model_14_init.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index ffb856a9b0..b49d975761 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -28,12 +28,15 @@ #include <arch/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h> +#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401 static void model_14_init(struct device *dev) { u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -75,9 +78,11 @@ static void model_14_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ |