diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-25 12:02:00 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-05 15:01:25 +0200 |
commit | df7ff31c5985d9c8e37c9f780c02c61e652181c0 (patch) | |
tree | 4c5cd7b2c6ee1eba6c6279b54c94f2bc5cf136fd /src/cpu/amd/agesa/family12 | |
parent | 13cf13587192ff82fbb3d060fe49fc677464c83b (diff) |
AGESA: Move romstage main entry under cpu
As we now apply asmlinkage attributes to romstage_main()
entry, also x86_64 passes parameters on the stack.
Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18624
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa/family12')
-rw-r--r-- | src/cpu/amd/agesa/family12/romstage.c | 51 |
1 files changed, 12 insertions, 39 deletions
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c index 67108b9093..13b9f06359 100644 --- a/src/cpu/amd/agesa/family12/romstage.c +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2017 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,26 +14,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> + #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> + #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> -#include <cpu/x86/bist.h> -#include <superio/smsc/kbc1100/kbc1100.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/agesa_helper.h> + #include "sb_cimx.h" #include "SbPlatform.h" -#include <arch/cpu.h> #include "platform_cfg.h" void asmlinkage early_all_cores(void) @@ -40,36 +32,17 @@ void asmlinkage early_all_cores(void) amd_initmmio(); } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void platform_once(struct sysinfo *cb) { - struct sysinfo *cb = NULL; - u32 val; - - post_code(0x35); + gpioEarlyInit(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - gpioEarlyInit(); - sb_poweron_init(); + sb_poweron_init(); - post_code(0x31); - - board_BeforeAgesa(cb); - - post_code(0x32); - post_code(0x33); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + board_BeforeAgesa(cb); +} +void agesa_main(struct sysinfo *cb) +{ post_code(0x36); agesawrapper_amdinitreset(); |