diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-17 20:18:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-19 09:20:22 +0000 |
| commit | d50cf23e43bb2e54210b2e719bbf53002814926b (patch) | |
| tree | ae17611aeca5d7f941cac99d48a23ff9d92dee15 /src/cpu/amd/agesa/family12 | |
| parent | 253cd5a7e6e2a651c2b0b85ebb6e9103567cae31 (diff) | |
{cpu,drivers}/amd: Replace MTRR addresses with macros
Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29173
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa/family12')
| -rw-r--r-- | src/cpu/amd/agesa/family12/fixme.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index 084cae8456..e97a819fda 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -98,7 +98,7 @@ void amd_initmmio(void) /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); } |