diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-06-20 19:56:06 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-06-28 23:09:25 +0200 |
| commit | 7c0c64e1033b4edf9a488e8e31948726ee17465e (patch) | |
| tree | 17d6b727807ed513c68ac00b9255577a86717b1b /src/cpu/amd/agesa/family12/Kconfig | |
| parent | 7c634ae8c18d1e311b5b96f09b5e6af23e57eaf7 (diff) | |
Addition of Family12/SB900 wrapper code
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.
Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa/family12/Kconfig')
| -rwxr-xr-x | src/cpu/amd/agesa/family12/Kconfig | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig new file mode 100755 index 0000000000..5679396f18 --- /dev/null +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -0,0 +1,74 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY12 + bool + select PCI_IO_CFG_EXT + +config CPU_ADDR_BITS + int + default 36 + depends on CPU_AMD_AGESA_FAMILY12 + +config CPU_SOCKET_TYPE + hex + default 0x10 + depends on CPU_AMD_AGESA_FAMILY12 + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + depends on CPU_AMD_AGESA_FAMILY12 + +config EXT_RT_TBL_SUPPORT + bool + default n + depends on CPU_AMD_AGESA_FAMILY12 + +config EXT_CONF_SUPPORT + bool + default n + depends on CPU_AMD_AGESA_FAMILY12 + +config CBB + hex + default 0x0 + depends on CPU_AMD_AGESA_FAMILY12 + +config CDB + hex + default 0x18 + depends on CPU_AMD_AGESA_FAMILY12 + +config XIP_ROM_BASE + hex + default 0xfff80000 + depends on CPU_AMD_AGESA_FAMILY12 + +config XIP_ROM_SIZE + hex + default 0x80000 + depends on CPU_AMD_AGESA_FAMILY12 + +config HAVE_INIT_TIMER + bool + default y + depends on CPU_AMD_AGESA_FAMILY12 + |