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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-21 07:37:13 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-05 15:00:23 +0200 |
| commit | 13cf13587192ff82fbb3d060fe49fc677464c83b (patch) | |
| tree | 231735af14e9c213ac7479ad5b832e4e5796b703 /src/cpu/amd/agesa/cache_as_ram.inc | |
| parent | b85ddc787ee2e82712b95b2eb3b90f4b56698e41 (diff) | |
AGESA: Move amd_initmmio() call
Function enables PCI MMCONF and XIP cache, it needs
to be called before giving platform any chance of
calling any PCI access functions.
Change-Id: Ic044d4df7b93667fa987c29c810d0bd826af87ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18623
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/amd/agesa/cache_as_ram.inc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index c0a69ec74a..b7619ff58a 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -108,19 +108,24 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: + + .code64 + + call early_all_cores + /* Pass the cpu_init_detected */ cvtsd2si %xmm1, %esi /* Pass the BIST result */ cvtsd2si %xmm0, %edi - - .code64 call cache_as_ram_main .code32 #else + call early_all_cores + /* Restore the BIST result */ cvtsd2si %xmm0, %edx |