diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-02 16:41:43 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-26 10:05:48 +0000 |
| commit | 63fac81fc80d701a785ed61a3b5738ea0a821169 (patch) | |
| tree | 7b50798c95fc1e3ec309351157197784e04131f8 /src/cpu/amd/agesa/Makefile.inc | |
| parent | 8bf978c2aa92aa194d74e6588344f579de5828de (diff) | |
AGESA: Implement POSTCAR_STAGE
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.
We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.
Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa/Makefile.inc')
| -rw-r--r-- | src/cpu/amd/agesa/Makefile.inc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index c8e125e445..f4ec2ce0b0 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,11 +24,13 @@ ifeq ($(CONFIG_AGESA_LEGACY), y) cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc else cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S -romstage-y += romstage.c +romstage-y += romstage.c mtrr_fixme.c endif romstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += heapmanager.c +postcar-y += cache_as_ram.S + ramstage-y += heapmanager.c ramstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += amd_late_init.c |