summaryrefslogtreecommitdiff
path: root/src/cpu/amd/Makefile.inc
diff options
context:
space:
mode:
authorSubrata Banik <subratabanik@google.com>2023-09-15 20:19:24 +0000
committerSubrata Banik <subratabanik@google.com>2023-09-22 06:55:42 +0000
commit6b62329cd682abf919d866cc259dd7d2c0f609da (patch)
tree6e342ff1f2cfab461b79bfb268a4404a3099dcf1 /src/cpu/amd/Makefile.inc
parent839c7f86044ab9e460d9ad905f77aa7f3f61aadb (diff)
mb/google/rex: Add new FMD for prod (QS) Meteor Lake silicon
Intel Meteor Lake QS silicon provides better size optimized pre-x86 reset blobs. This patch creates a new flash layout (FMD) for QS to accommodate those optimizations, and renames the existing FMD for ES (pre-prod) silicon. Comparative analysis between QS and ES flash layout is here: For QS silicon: - SI_ALL reduced from 9MB to 8MB. - SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI layout. - ME_RW_A/B reduce from ~4.5MB to 4MB. - Ensure RW-B slot is starting at 16MB boundary. - Unused space increased by 1MB. For ES silicon: - SI_ALL: 9MB - SI_BIOS: 23MB - ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH). - Unused space 3MB (for release) and 2MB (for debug) layout. Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Diffstat (limited to 'src/cpu/amd/Makefile.inc')
0 files changed, 0 insertions, 0 deletions