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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-09-07 01:54:23 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-09-07 17:40:32 +0000
commit2c482a969a546a70c2787d4d96d1ac212da11eff (patch)
tree2e255af6918f41ae63e185726ae7620a598fcc49 /src/cpu/allwinner/a10
parent4460703f59c58626c762a8a1244842b7a3efe0db (diff)
intel: Do not hardcode the position of mrc.cache
The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/allwinner/a10')
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