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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-28 15:10:28 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-03-29 22:28:44 +0100 |
| commit | 01c44000bedc571b10bdae7d0acfba079a131e42 (patch) | |
| tree | 305a9157208447bded08265d60dc5dd399b871db /src/cpu/allwinner/a10 | |
| parent | fccfee3bce901dfe78af8c36656f09973c2f3846 (diff) | |
cubieboard: Enable the SD controller and mux SD pins
This step needs to be done before calling any MMC functionality.
Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/allwinner/a10')
| -rw-r--r-- | src/cpu/allwinner/a10/clock.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 0be736cf34..0a9cfd6adf 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -66,6 +66,16 @@ /* DRAM_CLK values*/ #define DRAM_CTRL_DCLK_OUT (1 << 15) +/* SDx_CLK values */ +#define SDx_CLK_GATE (1 << 31) +#define SDx_CLK_SRC_MASK (3 << 24) +#define SDx_CLK_SRC_OSC24M (0 << 24) +#define SDx_CLK_SRC_PLL6 (1 << 24) +#define SDx_CLK_SRC_PLL5 (2 << 24) +#define SDx_RAT_EXP_N_MASK (3 << 16) +#define SDx_RAT_EXP_N(n) (((n) << 16) & SDx_RAT_EXP_N_MASK) +#define SDx_RAT_M_MASK (0xf << 0) +#define SDx_RAT_M(m) ((((m) - 1) << 0) & SDx_RAT_M_MASK) /** * \brief Clock gating definitions * |