arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
index 2ff88f528d..5082114d1b 100644
--- a/src/cpu/allwinner/a10/timer.c
+++ b/src/cpu/allwinner/a10/timer.c
@@ -24,13 +24,13 @@ void init_timer(void)
 {
 	u32 reg32;
 	/* Load the timer rollover value */
-	writel(0xffffffff, &tmr0->interval);
+	write32(&tmr0->interval, 0xffffffff);
 	/* Configure the timer to run from 24MHz oscillator, no prescaler */
 	reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
 	reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
 	reg32 |= TIMER_CTRL_RELOAD;
 	reg32 |= TIMER_CTRL_TMR_EN;
-	writel(reg32, &tmr0->ctrl);
+	write32(&tmr0->ctrl, reg32);
 }
 
 void udelay(unsigned usec)
@@ -61,6 +61,6 @@ void udelay(unsigned usec)
  */
 u8 a1x_get_cpu_chip_revision(void)
 {
-	writel(0, &timer_module->cpu_cfg);
+	write32(&timer_module->cpu_cfg, 0);
 	return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
 }