arm(64): Replace write32() and friends with writel()

This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:

@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)

This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.

BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.

Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 14 insertions, 14 deletions

diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c
index de24e03ec8..c1df4f427a 100644
--- a/src/cpu/allwinner/a10/raminit.c
+++ b/src/cpu/allwinner/a10/raminit.c
@@ -118,7 +118,7 @@ static void mctl_configure_hostport(void)
 	u32 i;
 
 	for (i = 0; i < 32; i++)
-		write32(hpcr_value[i], &dram->hpcr[i]);
+		writel(hpcr_value[i], &dram->hpcr[i]);
 }
 
 static void mctl_setup_dram_clock(u32 clk)
@@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk)
 		tmp_val = tmp_val * 9 - 200;
 		reg32 |= tmp_val << 8;
 		reg32 |= 0x8 << 24;
-		write32(reg32, &dram->drr);
+		writel(reg32, &dram->drr);
 	} else {
-		write32(0x0, &dram->drr);
+		writel(0x0, &dram->drr);
 	}
 }
 
@@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para)
 	a1x_gate_dram_clock_output();
 
 	/* select dram controller 1 */
-	write32(DRAM_CSEL_MAGIC, &dram->csel);
+	writel(DRAM_CSEL_MAGIC, &dram->csel);
 
 	mctl_itm_disable();
 	mctl_enable_dll0(para->tpr3);
@@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para)
 	reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
 	reg32 |= DRAM_DCR_CMD_RANK_ALL;
 	reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
-	write32(reg32, &dram->dcr);
+	writel(reg32, &dram->dcr);
 
 	/* dram clock on */
 	a1x_ungate_dram_clock_output();
@@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para)
 	reg32 = ((para->zq) >> 8) & 0xfffff;
 	reg32 |= ((para->zq) & 0xff) << 20;
 	reg32 |= (para->zq) & 0xf0000000;
-	write32(reg32, &dram->zqcr0);
+	writel(reg32, &dram->zqcr0);
 
 	/* set I/O configure register */
 	reg32 = 0x00cc0000;
 	reg32 |= (para->odt_en) & 0x3;
 	reg32 |= ((para->odt_en) & 0x3) << 30;
-	write32(reg32, &dram->iocr);
+	writel(reg32, &dram->iocr);
 
 	/* set refresh period */
 	dramc_set_autorefresh_cycle(para->clock);
 
 	/* set timing parameters */
-	write32(para->tpr0, &dram->tpr0);
-	write32(para->tpr1, &dram->tpr1);
-	write32(para->tpr2, &dram->tpr2);
+	writel(para->tpr0, &dram->tpr0);
+	writel(para->tpr1, &dram->tpr1);
+	writel(para->tpr2, &dram->tpr2);
 
 	if (para->type == DRAM_MEMORY_TYPE_DDR3) {
 		reg32 = DRAM_MR_BURST_LENGTH(0x0);
@@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para)
 		reg32 |= DRAM_MR_CAS_LAT(para->cas);
 		reg32 |= DRAM_MR_WRITE_RECOVERY(0x5);
 	}
-	write32(reg32, &dram->mr);
+	writel(reg32, &dram->mr);
 
-	write32(para->emr1, &dram->emr);
-	write32(para->emr2, &dram->emr2);
-	write32(para->emr3, &dram->emr3);
+	writel(para->emr1, &dram->emr);
+	writel(para->emr2, &dram->emr2);
+	writel(para->emr3, &dram->emr3);
 
 	/* set DQS window mode */
 	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);