cpu/allwinner/a10: Add minimal ramstage driver

Change-Id: I857755976b17b0e492c086162f395a77933eeed8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4698
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h
new file mode 100644
index 0000000000..45141fe5c0
--- /dev/null
+++ b/src/cpu/allwinner/a10/ram_segs.h
@@ -0,0 +1,30 @@
+/*
+ * How we use DRAM on Allwinner CPUs
+ *
+ * Copyright (C) 2014  Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <config.h>
+
+/*
+ * Put CBMEM at top of RAM
+ */
+static inline void *a1x_get_cbmem_top(void)
+{
+	return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20);
+}
+
+/*
+ * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region.
+ */
+static inline void *a1x_get_cbfs_cache_top(void)
+{
+	/* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */
+	return a1x_get_cbmem_top() - (16 << 20);
+}
+
+static inline void *a1x_get_cbfs_cache_base(void)
+{
+	return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE;
+}