arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index e7984dd328..c22b24273e 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph)
 	addr = (void *)A1X_CCM_BASE + (periph >> 5);
 	reg32 = read32(addr);
 	reg32 |= 1 << (periph & 0x1f);
-	writel(reg32, addr);
+	write32(addr, reg32);
 }
 
 /**
@@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph)
 	addr = (void *)A1X_CCM_BASE + (periph >> 5);
 	reg32 = read32(addr);
 	reg32 &= ~(1 << (periph & 0x1f));
-	writel(reg32, addr);
+	write32(addr, reg32);
 }
 
 /**
@@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p)
 	reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) |
 		  PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p));
 	reg32 |= PLL5_PLL_ENABLE;
-	writel(reg32, &ccm->pll5_cfg);
+	write32(&ccm->pll5_cfg, reg32);
 }
 
 /**
@@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits)
 	reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
 	reg32 &= ~CPU_CLK_SRC_MASK;
 	reg32 |= clksel_bits & CPU_CLK_SRC_MASK;
-	writel(reg32, &ccm->cpu_ahb_apb0_cfg);
+	write32(&ccm->cpu_ahb_apb0_cfg, reg32);
 }
 
 static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
@@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
 	reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK;
 	reg32 |= (ahb_exp << 4) & AHB_DIV_MASK;
 	reg32 |= (apb0_exp << 8) & APB0_DIV_MASK;
-	writel(reg32, &ccm->cpu_ahb_apb0_cfg);
+	write32(&ccm->cpu_ahb_apb0_cfg, reg32);
 }
 
 static void spin_delay(u32 loops)
@@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
 	change_sys_divisors(axi, ahb_exp, apb0_exp);
 
 	/* Configure PLL1 at the desired frequency */
-	writel(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
+	write32(&ccm->pll1_cfg, pll1_table[i].pll1_cfg);
 	spin_delay(8);
 
 	cpu_clk_src_switch(CPU_CLK_SRC_PLL1);