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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-05-21 13:29:45 +0100
committerMartin Roth <martinroth@google.com>2015-12-21 02:05:17 +0100
commit6b95406ff3d44679d2e0139236c134655b12b927 (patch)
tree03248c5604b395f791beaeaf3de050ffb4653ac9 /src/cpu/Makefile.inc
parentf6d3bd4815d2d442eb3cdf418ba3074134e5bd7d (diff)
imgtec/pistachio: DDR2, DDR3: DQS gate early
Switching on DQS Gate Early and DQS Gate Extension with 500R DQS/DSQN Resistors. This setup was recommended by Synopsys. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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