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| author | Patrick Huang <patrick.huang@amd.corp-partner.google.com> | 2023-03-21 16:35:11 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-27 12:05:52 +0000 |
| commit | b6436600ca9e5fb9197fb035bda5c8dfb0843ca3 (patch) | |
| tree | 51a07a7dd40b8dc7b2997d6d9f8a50f476657a42 /src/console | |
| parent | 25b5982d107b48642036c19c495364b72fed71ff (diff) | |
soc/amd/mendocino: Add UPDs for DPTC current limits
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC.
Make sure UPD parameterare are set to be aligned.
BUG=b:245942343
BRANCH=none
TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD.
Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/console')
0 files changed, 0 insertions, 0 deletions