diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-31 14:34:40 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-31 14:34:40 +0000 |
| commit | 5a1f5970857a5ad1fda0cf9d5945192408bf537b (patch) | |
| tree | b81a16a564c29788dcb6c306ea27855703d230de /src/console | |
| parent | b8ac05d187c6cc4e777c96d39e075c5d97d93ffc (diff) | |
This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.
While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
from romcc)
Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code
in cache_as_ram.inc)
Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/console')
| -rw-r--r-- | src/console/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/console/console.c | 46 |
2 files changed, 45 insertions, 3 deletions
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a5dc735369..8de1a7b46a 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -14,3 +14,5 @@ driver-$(CONFIG_CONSOLE_VGA) += vga_console.o driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o + +$(obj)/console/console.o : $(obj)/build.h diff --git a/src/console/console.c b/src/console/console.c index 4543b0c7b3..ace76d902c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -2,8 +2,12 @@ * Bootstrap code for the INTEL */ -#include <arch/io.h> #include <console/console.h> +#include <build.h> +#include <arch/hlt.h> + +#ifndef __PRE_RAM__ +#include <arch/io.h> #include <string.h> #include <pc80/mc146818rtc.h> @@ -86,6 +90,42 @@ void post_code(uint8_t value) void __attribute__((noreturn)) die(const char *msg) { printk(BIOS_EMERG, "%s", msg); - post_code(0xff); - while (1); /* Halt */ + //post_code(0xff); + for (;;) + hlt(); /* Halt */ +} + +#else + +void console_init(void) +{ + static const char console_test[] = + "\r\n\r\ncoreboot-" + COREBOOT_VERSION + COREBOOT_EXTRA_VERSION + " " + COREBOOT_BUILD + " starting...\r\n"; + print_info(console_test); +} + +void post_code(u8 value) +{ +#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 +#if CONFIG_SERIAL_POST==1 + print_emerg("POST: 0x"); + print_emerg_hex8(value); + print_emerg("\r\n"); +#endif + outb(value, 0x80); +#endif } + +void die(const char *str) +{ + print_emerg(str); + do { + hlt(); + } while(1); +} +#endif |