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authorSubrata Banik <subrata.banik@intel.com>2021-09-30 13:15:50 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-10-02 08:44:42 +0000
commit38abbdab71e6bf275c9c49748f1830576ddb2f22 (patch)
treea6c5a16af287b4cc3ce96e0464f7eb7e4a438245 /src/console
parentf576581954baa8df95e93bf136d1d2b0e8a7b646 (diff)
soc/intel/common/../cse: Avoid caching of CSE BAR
This patch ensures all attempts to read CSE BAR is performing PCI config space read and returning the BAR value rather than using cached value. This refactoring is useful to read BAR of all CSE devices rather than just HECI 1 alone. Additionally, change the return type of get_cse_bar() from `uintptr_t` to `void *` to avoid typecasting while calling read32/write32 functions. BUG=b:200644229 TEST=Able to build and boot ADLRVP where CSE is able to perform PCI enumeration and send the EOP message at post. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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