summaryrefslogtreecommitdiff
path: root/src/console/post.c
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2019-02-15 05:36:50 -0800
committerDuncan Laurie <dlaurie@chromium.org>2019-02-19 22:00:40 +0000
commit34745f613f4a2970b2298bd76bfaf737229a4a3a (patch)
tree4db539a93bfdd12f843b366673fae26a6eb45ae7 /src/console/post.c
parent04aae87da74a8c47abb46958384ef5632fec1e4a (diff)
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID was changed from 806EB to 806EC, include that as well. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 Reviewed-on: https://review.coreboot.org/c/31433 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/console/post.c')
0 files changed, 0 insertions, 0 deletions