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authorPatrick Georgi <patrick.georgi@secunet.com>2013-06-18 11:34:01 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2013-06-20 12:43:01 +0200
commit483ff8253943b134e5e07ac89d08e49fca1c28d8 (patch)
tree793b9e623695414b483e4190d257c2b3e14c8232 /src/console/cbmem_console.c
parent44c392f8c27a019ac0ac076c2e6b16d55c624c3b (diff)
sandybridge: Store MRC cache in CBFS
Location is hard-coded right now, which isn't optimal. It must be chip erase block aligned, which might fail on some flash chips (it's 64k aligned which should work for most cases). Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3497 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/console/cbmem_console.c')
0 files changed, 0 insertions, 0 deletions