diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2024-01-30 12:44:54 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-03-08 16:59:25 +0000 |
| commit | 1879b6a34a6e93a93d691a0d9f2457d6251a17c1 (patch) | |
| tree | cab0940a6f49d1cd2c8e2b75d194d0bfc45d2aaf /src/commonlib | |
| parent | 7eb014eba23b2141f262b7c7ba0172f16c759baa (diff) | |
drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It support 64-bits FSP but 64-bits support will be provided by
subsequent patch.
Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase.
[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf
[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/include/commonlib/console/post_codes.h | 14 | ||||
| -rw-r--r-- | src/commonlib/include/commonlib/timestamp_serialized.h | 5 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index c0b15c5910..d581bc487f 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -362,6 +362,20 @@ #define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3 /** + * \brief Before calling FSP Multiphase MemoryInit + * + * Going to call into FSP binary for Multiple phase MEM Init + */ +#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY 0xa4 + +/** + * \brief After calling FSP Multiphase MemoryInit + * + * FSP binary returned from Multiple phase MEM Init + */ +#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT 0xa5 + +/** * \brief Invalid or corrupt ROM * * Set if firmware failed to find or validate a resource that is stored in ROM. diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index e4439cd540..0ccb3b9394 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -138,6 +138,8 @@ enum timestamp_id { TS_FSP_END_OF_FIRMWARE_END = 961, TS_FSP_MULTI_PHASE_SI_INIT_START = 962, TS_FSP_MULTI_PHASE_SI_INIT_END = 963, + TS_FSP_MULTI_PHASE_MEM_INIT_START = 964, + TS_FSP_MULTI_PHASE_MEM_INIT_END = 965, TS_FSP_MEMORY_INIT_LOAD = 970, TS_FSP_SILICON_INIT_LOAD = 971, @@ -319,6 +321,9 @@ static const struct timestamp_id_to_name { TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_START, TS_FSP_MULTI_PHASE_SI_INIT_END, "calling FspMultiPhaseSiInit"), TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_END, 0, "returning from FspMultiPhaseSiInit"), + TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_START, TS_FSP_MULTI_PHASE_MEM_INIT_END, + "calling FspMultiPhaseMemInit"), + TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_END, 0, "returning from FspMultiPhaseMemInit"), TS_NAME_DEF(TS_FSP_ENUMERATE_START, TS_FSP_ENUMERATE_END, "calling FspNotify(AfterPciEnumeration)"), TS_NAME_DEF(TS_FSP_ENUMERATE_END, 0, "returning from FspNotify(AfterPciEnumeration)"), |