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authorAndrey Petrov <andrey.petrov@intel.com>2016-11-08 08:30:06 -0800
committerAaron Durbin <adurbin@chromium.org>2016-11-30 16:46:16 +0100
commitef9a9ea3b7585354d447ab0b3145e1b357226647 (patch)
treef669c9bf0b145e1212ac40cb33404c2f24de7bb5 /src/commonlib
parent4ed99ad067a7bd9f5ef6004c7b0e5f9f7edbe0d5 (diff)
soc/intel/common: Add save/restore for variable MRC data
Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/commonlib')
-rw-r--r--src/commonlib/include/commonlib/cbmem_id.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
index 0d2a7c351c..9fb1606528 100644
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -41,6 +41,7 @@
#define CBMEM_ID_MMA_DATA 0x4D4D4144
#define CBMEM_ID_MPTABLE 0x534d5054
#define CBMEM_ID_MRCDATA 0x4d524344
+#define CBMEM_ID_VAR_MRCDATA 0x4d524345
#define CBMEM_ID_MTC 0xcb31d31c
#define CBMEM_ID_NONE 0x00000000
#define CBMEM_ID_PIRQ 0x49525154
@@ -92,6 +93,7 @@
{ CBMEM_ID_MMA_DATA, "MMA DATA " }, \
{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
+ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \
{ CBMEM_ID_MTC, "MTC " }, \
{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
{ CBMEM_ID_POWER_STATE, "POWER STATE" }, \