diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-06-10 14:39:01 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-06-16 22:42:05 +0000 |
| commit | d742b5e40c76a0855d9fcbe67beff0d0d5fd1648 (patch) | |
| tree | 2a2cd4af2dae6a641d1125176adb8d84c429e69c /src/commonlib | |
| parent | c545baaf476016c1c136c3c88214c3c4252d4059 (diff) | |
timestamp,amd/common/apob_cache: Add timestamps for APOB
Updating the APOB takes a considerable amount of time. I decided to be
granular and split out the operations so we know when we read vs read +
erase + write.
BUG=b:179092979
TEST=Boot guybrush and dump timestamps
3:after RAM initialization 3,025,425 (44)
920:starting APOB read 3,025,430 (5)
921:starting APOB erase 3,025,478 (48)
922:starting APOB write 3,027,727 (2,249)
923:finished APOB 3,210,965 (183,238)
4:end of romstage 3,210,971 (6)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I08e371873112e38f623f452af0eb946f5471c399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/include/commonlib/timestamp_serialized.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index a69e1d3539..1351afacf3 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -78,7 +78,7 @@ enum timestamp_id { TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, - /* 900-920 reserved for vendorcode extensions (900-940: AMD AGESA) */ + /* 900-940 reserved for vendorcode extensions (900-940: AMD) */ TS_AGESA_INIT_RESET_START = 900, TS_AGESA_INIT_RESET_DONE = 901, TS_AGESA_INIT_EARLY_START = 902, @@ -99,6 +99,10 @@ enum timestamp_id { TS_AGESA_S3_LATE_DONE = 917, TS_AGESA_S3_FINAL_START = 918, TS_AGESA_S3_FINAL_DONE = 919, + TS_AMD_APOB_READ_START = 920, + TS_AMD_APOB_ERASE_START = 921, + TS_AMD_APOB_WRITE_START = 922, + TS_AMD_APOB_DONE = 923, /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ TS_ME_INFORM_DRAM_WAIT = 940, @@ -222,7 +226,7 @@ static const struct timestamp_id_to_name { { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, { TS_START_KERNEL, "jumping to kernel" }, - /* AMD AGESA related timestamps */ + /* AMD related timestamps */ { TS_AGESA_INIT_RESET_START, "calling AmdInitReset" }, { TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" }, { TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" }, @@ -243,6 +247,10 @@ static const struct timestamp_id_to_name { { TS_AGESA_S3_LATE_DONE, "back from AmdS3LateRestore" }, { TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" }, { TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" }, + { TS_AMD_APOB_READ_START, "starting APOB read" }, + { TS_AMD_APOB_ERASE_START, "starting APOB erase" }, + { TS_AMD_APOB_WRITE_START, "starting APOB write" }, + { TS_AMD_APOB_DONE, "finished APOB" }, /* Intel ME related timestamps */ { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, |