summaryrefslogtreecommitdiff
path: root/src/commonlib
diff options
context:
space:
mode:
authorWonkyu Kim <wonkyu.kim@intel.com>2020-05-20 13:25:04 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:10:57 +0000
commitb4d7116a740b2847ef112cc1954462dac0b4cf85 (patch)
treefd3a6b827e1dad96e3dbb2f8ead747daef37e488 /src/commonlib
parent165efa1b863ad8c35646beda6ddd76075c5674a2 (diff)
soc/intel/tigerlake: Delete unused configuration
Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG:b:151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/commonlib')
0 files changed, 0 insertions, 0 deletions