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| author | Peichao Wang <peichao.wang@bitland.corp-partner.google.com> | 2019-09-09 09:10:54 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-10 12:11:30 +0000 |
| commit | 632283092c168f2465acbe56cf0a8bb7fc17e93f (patch) | |
| tree | c60ecdc9ea74b7d1b1de987001c2cb68874462da /src/commonlib/storage | |
| parent | 203061c24aba584edbd54dfe634ca1038c5e1ac1 (diff) | |
mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock
Tune I2C bus 1, 2 and 3 clock and make them meet spec.
BUG=b:140665478
TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock
frequency less than 400KHz
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/commonlib/storage')
0 files changed, 0 insertions, 0 deletions