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author | Keno Fischer <keno@juliacomputing.com> | 2019-06-07 01:55:56 -0400 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2019-06-07 10:08:35 +0000 |
commit | 1044ebaa06d8932564fa3ca3b0c4fbd25a63d992 (patch) | |
tree | 73f92e9fd668c4206bb1c5a314c1633ef331b02a /src/commonlib/storage | |
parent | 55c577717097ecd9bb5f2d67ac7ab32f28c85ade (diff) |
soc/intel: Add some missing MCH PCIe IDs
These are documented in the Intel Datasheet entitled
"6th Generation IntelĀ® Processor Datasheet for S-Platforms"
"6th Generation IntelĀ® Processor Datasheet for H-Platforms" (Volume 2)
Without them, coreboot fails to properly inform the payload of the
amount of available memory.
Signed-off-by: Keno Fischer <keno@juliacomputing.com>
Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/commonlib/storage')
0 files changed, 0 insertions, 0 deletions