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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:12:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:37:47 +0000 |
| commit | d2bbc68fa32ec60f8aa83870559beadbef0d1c9f (patch) | |
| tree | 801c1c9eb4ff7697ba57f20fe66567818d7bd40c /src/commonlib/storage/sd.c | |
| parent | 066e61f3ea1f65012b14467412e6b17351c87dc6 (diff) | |
soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/commonlib/storage/sd.c')
0 files changed, 0 insertions, 0 deletions