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| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2022-07-21 15:40:03 -0700 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-28 14:57:54 +0000 |
| commit | 117770d32468e63df37aee1c041b5dc7cc1d56d2 (patch) | |
| tree | 020f66d01ab7c7f6dc28f55c49439bf80c0f59ce /src/commonlib/mem_pool.c | |
| parent | ccbf27cbe7f9cd78461a946cf92cc97d652d19dd (diff) | |
soc/intel/alderlake: Enable Energy/Performance Bias control
According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL
must be set to be able to set the Energy/Performance Bias using MSR
IA32_ENERGY_PERF_BIAS.
Note that since this bit was not set until this patch, the
`set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in
`soc_core_init()` was systematically failing.
BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/commonlib/mem_pool.c')
0 files changed, 0 insertions, 0 deletions