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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-07-18 13:38:32 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:33:08 +0000 |
| commit | a76a64833bb02c342f6190231ef38ac39151da45 (patch) | |
| tree | 79bf3ee0c7cb2d2edc2fda703166ecca54b28a9a /src/commonlib/fsp_relocate.c | |
| parent | 6489a19c780126a92931fc9b20a617cedbba7b6b (diff) | |
soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/commonlib/fsp_relocate.c')
0 files changed, 0 insertions, 0 deletions