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authorEric Biederman <ebiederm@xmission.com>2003-05-19 19:16:21 +0000
committerEric Biederman <ebiederm@xmission.com>2003-05-19 19:16:21 +0000
commit526855741b6abb970024366316b941fb6b3d2cb6 (patch)
tree7da1560ec08c513a23b23704cae3637925e5bd68 /src/boot
parent49cf5967ce31af37e61d59a00939f50bc4256761 (diff)
- Cleanups on the romcc side including a pci interface that uses
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/boot')
-rw-r--r--src/boot/hardwaremain.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index d64acef05b..4e7b9e379e 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -161,7 +161,7 @@ void hardwaremain(int boot_complete)
#endif
#if 1
- // pick how to scan the bus. This is first so we can get at memory size.
+ /* pick how to scan the bus. This is first so we can get at memory size. */
printk_info("Finding PCI configuration type.\n");
pci_set_method();
post_code(0x5f);
@@ -170,13 +170,15 @@ void hardwaremain(int boot_complete)
#endif
dev_enumerate();
post_code(0x66);
- // Now do the real bus
- // we round the total ram up a lot for thing like the SISFB, which
- // shares high memory with the CPU.
+ /* Now do the real bus.
+ * We round the total ram up a lot for thing like the SISFB, which
+ * shares high memory with the CPU.
+ */
dev_configure();
post_code(0x88);
dev_enable();
+
dev_initialize();
post_code(0x89);
#endif