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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-09-14 08:27:50 -0700
committerMartin Roth <martinroth@google.com>2018-09-15 12:43:26 +0000
commitc75f2d811933051c991d71f39aa94b43063ec479 (patch)
treef6e5758df0203843ddb24b3c7d305582da276943 /src/arch
parentded91fffb833823ea7d71654c1e10696eba0d419 (diff)
arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706
There are 8 possible BERT context errors, with table ctx_names being a table to print their names. Thus the table is supposed to have 8 elements, and indeed it has 8 lines... but some lines are missing commas, and when compiling it becomes a 5 element table. Add the commas at the appropriate places. BUG=b:115719190 TEST=none. Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/acpi_bert_storage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index 82ecc5f59f..961faa6118 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -311,9 +311,9 @@ cper_ia32x64_context_t *new_cper_ia32x64_ctx(
"MSR Registers",
"32-bit Mode Execution",
"64-bit Mode Execution",
- "FXSAVE"
- "32-bit Mode Debug"
- "64-bit Mode Debug"
+ "FXSAVE",
+ "32-bit Mode Debug",
+ "64-bit Mode Debug",
"Memory Mapped"
};