diff options
author | Felix Singer <felixsinger@posteo.net> | 2022-01-03 19:01:06 +0100 |
---|---|---|
committer | Felix Singer <felixsinger@posteo.net> | 2022-07-30 00:11:36 +0000 |
commit | 311981ef4886ff9b32985d6847748f036ce9db16 (patch) | |
tree | 90745b1d99fa04e1e6fb34a53603e559833d6125 /src/arch | |
parent | b4a7f7443645b279f8935466d679caeebb637a95 (diff) |
arch/x86/acpi: Replace And() with ASL 2.0 syntax
Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/x86/acpi/debug.asl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index 728193e44f..70fd2ecb53 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -41,9 +41,9 @@ Method(DINI) */ Method(THRE) { - and(CLSR, 0x20, local0) + local0 = CLSR & 0x20 while (local0 == 0) { - and(CLSR, 0x20, local0) + local0 = CLSR & 0x20 } } @@ -75,7 +75,7 @@ Method(OUTC, 1) */ Method(DBGN, 1) { - and(Arg0, 0x0f, Local0) + Local0 = Arg0 & 0x0f if (Local0 < 10) { Local0 += 0x30 } else { |