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| author | Ronald G Minnich <rminnich@gmail.com> | 2024-03-15 21:56:20 -0700 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2024-03-22 23:01:48 +0000 |
| commit | 200f7b7ee13b98d726bd0e5de2792a14c558a7ea (patch) | |
| tree | 3df0dfd97c06196af2a2d92aef7e88912f088e4b /src/arch | |
| parent | 87fa1d07b57a8087da031e3db72695f0547db0c9 (diff) | |
arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG
Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.
The SiFive FU540 and FU740 do not support this register;
set the variable to n for those parts.
Add constants for this new CSR.
Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/riscv/Kconfig | 9 | ||||
| -rw-r--r-- | src/arch/riscv/include/arch/encoding.h | 4 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 971dda3160..b570b0147c 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -110,4 +110,13 @@ config RISCV_USE_ARCH_TIMER config RISCV_WORKING_HARTID int +# Newer SoC have the menvconfig register. +# Very few SOC do not have this. +# Older SoC, such as the SiFive FU[57]40, that +# do not have this register, should set this +# to n. +config RISCV_SOC_HAS_MENVCFG + bool + default y + endif # if ARCH_RISCV diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h index 4f01e5ce97..6ab38bb9e7 100644 --- a/src/arch/riscv/include/arch/encoding.h +++ b/src/arch/riscv/include/arch/encoding.h @@ -800,6 +800,8 @@ #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 +#define CSR_MENVCFG 0x30a +#define CSR_MENVCFGH 0x31a #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -1292,6 +1294,8 @@ DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(menvcfg, CSR_MENVCFG) +DECLARE_CSR(menvcfgh, CSR_MENVCFGH) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) |