summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorMike Banon <mikebdp2@gmail.com>2018-08-18 00:43:05 +0300
committerMartin Roth <martinroth@google.com>2018-08-20 17:24:14 +0000
commit0e596ae76033eee91fdd791b183378d9fd7cf79f (patch)
tree62367a0f8dd8fa1df1bd39686b98cd6fb2e46dcf /src/arch
parentcc11c97b70f3844d1f5707401a5d473c91f704ce (diff)
vendorcode/amd/agesa/f15tn: add Richland RL-A1 to the equivalence table
This small change is required for the successful loading of microcode from F15TnMicrocodePatch0600110F_Enc.c for the Richland RL-A1 CPUs, such as A10-5750M found at coreboot-supported Lenovo G505S laptop. Richland RL-A1 and Trinity TN-A1 CPUs are using the same microcode, so the Richland RL-A1 IDs should be added to this equivalence table. Function `GetPatchEquivalentId()` in `src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c` goes through the equivalence table like below. for (i = 0; i < (EquivalencyEntries * 2); i += 2) { // check for equivalence if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) { *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1]; return (TRUE); } } Change-Id: I7a68f2fef74fb4c578c47645f727a9ed45526f69 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28204 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: <awokd@danwin1210.me> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions