diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:28:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:06:39 +0000 |
| commit | 0949e739066c3509e05db2b9ed71cefaaa62205f (patch) | |
| tree | 797d772f524dd668689f8c2813f3b052e84de434 /src/arch | |
| parent | 6c3ece9c9ef73db5c0e02cc5a41c98f46b86c3e9 (diff) | |
src/acpi to src/lib: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/armv7/cpu.S | 2 | ||||
| -rw-r--r-- | src/arch/arm64/include/arch/asm.h | 2 | ||||
| -rw-r--r-- | src/arch/riscv/fit_payload.c | 2 | ||||
| -rw-r--r-- | src/arch/riscv/opensbi.c | 2 | ||||
| -rw-r--r-- | src/arch/x86/c_start.S | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index c53119c8d1..bc3ebd90a0 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -16,7 +16,7 @@ * the LSB of the set field, but the latter contains the LSB of the way field * minus the highest valid set field... such that when you subtract it from a * [way:0:level] field you end up with a [way - 1:highest_set:level] field - * through the magic of double subtraction. It's quite ingenius, really. + * through the magic of double subtraction. It's quite ingenious, really. * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without * needing to write to memory. * diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index e6246c39da..df5952a576 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -19,7 +19,7 @@ .size name, .-name /* - * Certain SoCs have an alignment requiremnt for the CPU reset vector. + * Certain SoCs have an alignment requirement for the CPU reset vector. * Align to a 64 byte typical cacheline for now. */ #define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index abce57ee08..f7f4106cae 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -7,7 +7,7 @@ #include <fit.h> #include <endian.h> -/* Implements a Berkley Boot Loader (BBL) compatible payload loading */ +/* Implements a Berkeley Boot Loader (BBL) compatible payload loading */ #define MAX_KERNEL_SIZE (64*MiB) diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index e719560db3..3a738ec83a 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -2,7 +2,7 @@ #include <sbi/fw_dynamic.h> #include <arch/boot.h> -/* DO NOT INLCUDE COREBOOT HEADERS HERE */ +/* DO NOT INCLUDE COREBOOT HEADERS HERE */ void run_opensbi(const int hart_id, const void *fdt, diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a4a7b28cbb..cb7d5045ff 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -217,7 +217,7 @@ SetCodeSelector: # use iret to jump to a 64-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp mov %ss, %ax # need to push ss.. - push %rax # push ss instuction not valid in x64 mode, + push %rax # push ss instruction not valid in x64 mode, # so use ax push %rsp pushfq |