diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-03-26 21:34:01 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-29 21:12:54 +0100 |
| commit | e85f4eb1b0f63535ceb36315712a03d7d7f656ac (patch) | |
| tree | 1d9b658ff09edb5ac35c63c24bb96c51e47c3ae6 /src/arch | |
| parent | dc82fc563486794005ada364f498167df9b686d6 (diff) | |
armv7: update sync barrier usage in dcache_op_set_way()
This moves the dsb() before the loop to sync any outstanding memory
accesses, and adds an isb() after the loop to ensure all outstanding
instructions are completed.
Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2929
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/armv7/lib/cache.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index d65e021623..c7283f14cf 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -111,6 +111,8 @@ static void dcache_op_set_way(enum dcache_op op) /* FIXME: do we need to use CTR.DminLine here? */ linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + dsb(); + /* * Set/way operations require an interesting bit packing. See section * B4-35 in the ARMv7 Architecture Reference Manual: @@ -144,8 +146,7 @@ static void dcache_op_set_way(enum dcache_op op) } } } - - dsb(); + isb(); } static void dcache_foreach(enum dcache_op op) |