diff options
| author | Julius Werner <jwerner@chromium.org> | 2017-07-25 13:55:43 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2018-02-02 22:19:37 +0000 |
| commit | 91ebbfdc5c7b99abc5391b3938367747b1bfc53b (patch) | |
| tree | 82d264ce13664b9b449704929233379ce68ae3c1 /src/arch | |
| parent | 89c2e7f77de98a89bfe57a8e40bfb99ced2bb2e3 (diff) | |
arm64: Pass COREBOOT flag to ARM TF, always enable logging
This patch changes the way coreboot builds ARM TF to pass the new
COREBOOT flag introduced with the following pull request:
https://github.com/ARM-software/arm-trusted-firmware/pull/1193
Since the new coreboot support code supports the CBMEM console, we need
to always enable LOG_LEVEL INFO. Supporting platforms will parse the
coreboot table to conditionally enable the serial console only if it was
enabled in coreboot as well.
Also remove explicit cache flushes of some BL31 parameters. Turns out we
never really needed these because we already flush the whole cache when
disabling the MMU, and we were already not doing it for most parameters.
Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm64/Makefile.inc | 16 | ||||
| -rw-r--r-- | src/arch/arm64/arm_tf.c | 5 |
2 files changed, 13 insertions, 8 deletions
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 92b26f5cd3..d9a73bd7c0 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -146,14 +146,20 @@ ifeq ($(V),1) BL31_MAKEARGS += V=1 endif -# Build ARM TF in debug mode (with serial output) if coreboot uses serial -ifeq ($(CONFIG_CONSOLE_SERIAL),y) +# Build ARM TF in debug mode (with assertions) if coreboot has hard assertions +ifeq ($(CONFIG_FATAL_ASSERTS),y) BL31_MAKEARGS += DEBUG=1 -else -# Turn off NOTICE messages from BL31 if coreboot does not use serial -BL31_MAKEARGS += LOG_LEVEL=0 endif # CONFIG_CONSOLE_SERIAL +# ARM TF's VERBOSE (50) is *very* spammy, so default to INFO (40) +BL31_MAKEARGS += LOG_LEVEL=40 + +# Always enable crash reporting, even on a release build +BL31_MAKEARGS += CRASH_REPORTING=1 + +# Enable coreboot-specific features like CBMEM console support +BL31_MAKEARGS += COREBOOT=1 + # Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index e976e34be0..69e83c10fe 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -81,11 +81,10 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) bl33_ep_info.spsr = payload_spsr; bl33_ep_info.args.arg0 = payload_arg0; - /* May update bl31_params if necessary. Must flush all added structs. */ + /* May update bl31_params if necessary. */ void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params); - dcache_clean_by_mva(&bl31_params, sizeof(bl31_params)); - dcache_clean_by_mva(&bl33_ep_info, sizeof(bl33_ep_info)); + /* MMU disable will flush cache, so passed params land in memory. */ raw_write_daif(SPSR_EXCEPTION_MASK); mmu_disable(); bl31_entry(&bl31_params, bl31_plat_params); |