x86: link romstage like the other architectures

All the other architectures are using the memlayout
for linking romstage. Use that same method on x86
as well for consistency.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.

Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11510
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 26 insertions, 41 deletions

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3c1871e6e7..0315798a51 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-srcs += $(src)/arch/x86/romstage.ld
-romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
+romstage-y += romstage.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs))
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
-	cat $^ >> $@.tmp
+	cat $< >> $@.tmp
 	mv $@.tmp $@
 
 $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index dd6cb271fa..55547adcd4 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -17,9 +17,15 @@
  * Foundation, Inc.
  */
 
+#include <rules.h>
+
 PHDRS
 {
 	to_load PT_LOAD;
 }
 
+#if ENV_RAMSTAGE
 ENTRY(_start)
+#elif ENV_ROMSTAGE
+ENTRY(protected_start)
+#endif
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 54b8b4a308..91cfc8e064 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -20,6 +20,12 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-/* Currently empty to satisfy common arch requirements. */
+#include <rules.h>
+
+#if ENV_ROMSTAGE
+/* No .data or .bss in romstage. Cache as ram is handled separately. */
+#define ARCH_STAGE_HAS_DATA_SECTION 0
+#define ARCH_STAGE_HAS_BSS_SECTION 0
+#endif
 
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index cc0142eb80..d6d1b9c684 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2006 Advanced Micro Devices, Inc.
  * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,52 +19,25 @@
  * Foundation, Inc.
  */
 
-TARGET(binary)
+#include <memlayout.h>
+#include <arch/header.ld>
+
 SECTIONS
 {
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(4);
-		_cbmem_init_hooks = .;
-		KEEP(*(.rodata.cbmem_init_hooks));
-		_ecbmem_init_hooks = .;
-		*(.rodata);
-		*(.rodata.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
 
 	. = CONFIG_DCACHE_RAM_BASE;
 	.car.data . (NOLOAD) : {
 		_car_data_start = .;
 #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
-		_timestamp = .;
-		. = . + 0x100;
-		_etimestamp = .;
+		TIMESTAMP(., 0x100)
 #endif
 		*(.car.global_data);
+		. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
 		_car_data_end = .;
-		/* The preram cbmem console area comes last to take advantage
-		 * of a zero-sized array to hold the memconsole contents.
-		 * However, collisions within the cache-as-ram region cannot be
-		 * statically checked because the cache-as-ram region usage is
-		 * cpu/chipset dependent. */
-		_preram_cbmem_console = .;
-		_epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00);
+
+		PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
 	}
 
 	/* Global variables are not allowed in romstage