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authorArthur Heymans <arthur@aheymans.xyz>2021-01-04 12:49:39 +0100
committerArthur Heymans <arthur@aheymans.xyz>2021-01-24 15:54:22 +0000
commit7a5c3696140dc839cb709adc3ebac58821efd786 (patch)
treeb40c2b3fdfec510f3118ae443cacdc32c546cabe /src/arch
parent9789689e41c9f560e1f0f8796485d3a68f7c2cb4 (diff)
soc/intel/xeon_sp/cpx: Account for 'rc' heap manager
The xeon_sp/cpx has a second 'rc' heap inside FSP-M that is statically allocated at the start of CAR. This breaks FSP 2.0 specification. This can be worked around in the linker scripts to make sure coreboot and FSP-M don't fight over the same memory. Tested - on ocp/deltalake: boot and the "Smashed stack detected in romstage!" message at the end of romstage is gone. - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I6d02b8a46a2a8ef00f34d8f257595d43f5d3d590 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/car.ld7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 63145f153e..68144c9d43 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -7,6 +7,7 @@
. = CONFIG_DCACHE_RAM_BASE;
.car.data . (NOLOAD) : {
_car_region_start = . ;
+ . += CONFIG_FSP_M_RC_HEAP_SIZE;
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
@@ -83,6 +84,12 @@
_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start)
- CONFIG_FSP_T_RESERVED_SIZE;
}
+
+. = _car_region_start;
+.car.fspm_rc_heap . (NOLOAD) : {
+. += CONFIG_FSP_M_RC_HEAP_SIZE;
+}
+
. = _car_region_end;
.car.mrc_var . (NOLOAD) : {
. += CONFIG_DCACHE_RAM_MRC_VAR_SIZE;