diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-09-16 16:15:14 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-19 17:01:55 +0200 |
| commit | 6b0cebccc4cfb99bb20f163de0f83af0c143c35a (patch) | |
| tree | 2c4a34d0ec421c18c0a35ab4ab182e36074d53c1 /src/arch/x86 | |
| parent | c701393e207cd09c6ce232960c7c647bef27055f (diff) | |
arch/x86: move postcar main logic into C
The console_init(), MTRR printing, and loading ramstage
logic was previously all in assembly. Move that logic
into C code so that future features can more easily be
added into the postcar boot flow.
BUG=chrome-os-partner:57513
Change-Id: I332140f569caf0803570fd635d894295de8c0018
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16618
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/arch/x86/exit_car.S | 14 | ||||
| -rw-r--r-- | src/arch/x86/postcar.c | 31 |
3 files changed, 34 insertions, 12 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 38a2a8ccba..8357588b3a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -287,6 +287,7 @@ postcar-y += memmove.c postcar-y += memset.c postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c +postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c LDFLAGS_postcar += -Map $(objcbfs)/postcar.map diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index ca9b70e663..5c62c92af8 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -26,11 +26,6 @@ stack_top: .text .global _start _start: -#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE) - /* Enable the console */ - call console_init -#endif /* CONFIG_POSTCAR_CONSOLE */ - /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car @@ -113,13 +108,8 @@ _start: wrmsr #endif /* CONFIG_SOC_SETS_MSRS */ - /* Display the MTRRs */ -#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE) - call soc_display_mtrrs -#endif /* CONFIG_POSTCAR_CONSOLE */ - - /* Load and run ramstage. */ - call copy_and_run + /* Call into main for postcar. */ + call main /* Should never return. */ 1: jmp 1b diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c new file mode 100644 index 0000000000..8c3ea43f46 --- /dev/null +++ b/src/arch/x86/postcar.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <main_decl.h> +#include <program_loading.h> +#include <soc/intel/common/util.h> + +void main(void) +{ + console_init(); + + /* Display the MTRRs */ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + soc_display_mtrrs(); + + /* Load and run ramstage. */ + run_ramstage(); +} |