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authorArthur Heymans <arthur@aheymans.xyz>2019-06-05 13:36:55 +0200
committerNico Huber <nico.h@gmx.de>2019-06-17 08:15:04 +0000
commit01c83a2e9975f71d53772a535cf13d3e76a46827 (patch)
treed907f491291eb8d16b6394fc831bd13af23c5422 /src/arch/x86
parent14774769daae489834473457712cd4c635ac1fbd (diff)
3rdparty/blobs: Update submodule, SNB improvements
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired) This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB. This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region. TESTED on T520 (boots and resumes from S3 with mrc.bin). Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/car.ld7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 29b3600bbe..5802b02896 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -91,13 +91,6 @@
_car_global_end = .;
_car_relocatable_data_end = .;
-#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && !CONFIG(USE_NATIVE_RAMINIT)
- . = ABSOLUTE(0xff7e1000);
- _mrc_pool = .;
- . += 0x5000;
- _emrc_pool = .;
-#endif
-
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .;
_car_stack_end = _car_region_end;