diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2019-02-19 13:39:56 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-26 11:14:49 +0000 |
| commit | db561e6e3910b25d9314ba8b343c4387396c2f3f (patch) | |
| tree | ed91ef92aacdaa9f09a2d806012f3fe004198370 /src/arch/x86 | |
| parent | bd660e23382a74b399fa25ca01b9a9cd9c7683e9 (diff) | |
acpi: Sort the reported APIC-IDs in the MADT table
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, the OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
environment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.
Though there is a way to discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.
Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/acpi.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f4c7d86dc0..e06c3ad71b 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -8,7 +8,7 @@ * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, * Raptor Engineering - * Copyright (C) 2016-2017 Siemens AG + * Copyright (C) 2016-2019 Siemens AG * * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions @@ -48,6 +48,7 @@ #include <cpu/cpu.h> #include <cbfs.h> #include <version.h> +#include <commonlib/sort.h> u8 acpi_checksum(u8 *table, u32 length) { @@ -149,7 +150,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; - int index = 0; + int index, apic_ids[CONFIG_MAX_CPUS], num_cpus = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || @@ -158,9 +159,14 @@ unsigned long acpi_create_madt_lapics(unsigned long current) } if (!cpu->enabled) continue; + if (num_cpus >= ARRAY_SIZE(apic_ids)) + break; + apic_ids[num_cpus++] = cpu->path.apic.apic_id; + } + bubblesort(apic_ids, num_cpus, NUM_ASCENDING); + for (index = 0; index < num_cpus; index++) { current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, cpu->path.apic.apic_id); - index++; + index, apic_ids[index]); } return current; |