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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-08 10:40:02 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-01-06 16:48:09 +0000
commit8d0e77bbd4145e138ff43951c8543cea2c3dfd50 (patch)
tree8d6d61ada604acf62824d08a6185d436ce399401 /src/arch/x86
parent7fff266b0745b2d482961b2e35a568f202e92aec (diff)
soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/arch/x86')
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