diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-01-09 21:36:04 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-13 11:16:26 +0000 |
| commit | 31b2f8f1d018262428832fba6c6522e394a2aa2a (patch) | |
| tree | c327dd45b57dbd1c3ebf95ff119eabbcf8bad952 /src/arch/x86 | |
| parent | 6716babee5a64cbf3674a13656e5a4179c5cb331 (diff) | |
arch/x86/cf9_reset: Fix typo
Change-Id: I4a8d29ab647837965e5341d019664f0ed401639a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/cf9_reset.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index ccfaa7d9f8..d93bed74a4 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -35,7 +35,7 @@ void do_system_reset(void) * A full reset in terms of the CF9 register triggers a power cycle * (i.e. S0 -> S5 -> S0 transition). Thus, it could be called a * "cold reset". - * Note: Not all x86 implementations comply with this defitinion, + * Note: Not all x86 implementations comply with this definition, * some may require additional configuration to power cycle. */ void do_full_reset(void) |