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authorAaron Durbin <adurbin@chromium.org>2013-06-11 16:36:37 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 21:45:28 +0200
commit32ab283b1086ef53fadcd4be92df6e41c5d06438 (patch)
treeb6abc67d0383413dc091d8d6d9639916ddf53066 /src/arch/x86
parente221aad27fb860f31be089180d920df9d2243ae2 (diff)
cpu: Add CPU microcode file to cbfs with 16-byte alignment
On x86 there is a 16-byte alignment requirement for the addresses containing the CPU microcode. The cbfs files containing the microcode are used in memory-mapped fashion when loading new mircocode. Therefore, the data payload's address/offset of a cbfs file in flash dictates the resulting alignment. Fix this by processing the CPU microcode cbfs file separately as it uses $(CBFSTOOL) to find the proper location within the provided rom image. Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/Makefile.inc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7f1b7b2968..0faf140a47 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -61,11 +61,12 @@ prebuild-files = \
$(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&)
prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
-$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL)
+$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
$(CBFSTOOL) $@.tmp create -m x86 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
-B $(objcbfs)/bootblock.bin -a 64 \
-o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
$(prebuild-files) true
+ $(call add-cpu-microcode-to-cbfs,$@.tmp)
mv $@.tmp $@
else
.PHONY: $(obj)/coreboot.pre1