diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 03:02:40 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 03:02:40 +0000 |
| commit | 19245c94c8d8e293fdb7e4c734ef0abccf601ca2 (patch) | |
| tree | dcd454b470b68ddfd30169a3faf61f5c4bc03d70 /src/arch/x86 | |
| parent | 9cbcf1ada4ac32b3fb638b0a002f9cb7ae003072 (diff) | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it for good mesure.
If I understood BKDG fam10 CPUs never need a software initiated vid transition,
because the hardware knows what to do when you just request
a Pstate change if the cpu is properly configured. In fact
unifying a little what PVI and SVI do was better for my board (SVI).
So I drop transitionVid, which I didn't understand either (why
did it have a case for PVI if it is never called for PVI ?
Why did the PVI case distinguigh cpu or nb when PVI is
theoretically single voltage plane ? ).
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/x86')
0 files changed, 0 insertions, 0 deletions