summaryrefslogtreecommitdiff
path: root/src/arch/x86/wakeup.S
diff options
context:
space:
mode:
authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-03-05 00:41:14 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-10 10:02:19 +0000
commitdcd3d072d4760d9040b61d34c5ee6663a963fb54 (patch)
tree3f13eb7f90713fdf3e544482b7dc4b39c894f45c /src/arch/x86/wakeup.S
parent2b4ded0be8c1c01aba566bb4bbccf5169ce133f7 (diff)
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86/wakeup.S')
0 files changed, 0 insertions, 0 deletions