arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK

When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for
a chipset specific verstage entry point because cache-as-ram has
already been initialized. Therefore, provide a default entry point
for verstage in that environment.

Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14971
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c
new file mode 100644
index 0000000000..a44bf0fa01
--- /dev/null
+++ b/src/arch/x86/verstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Provide an entry point for verstage when it's a separate stage. */
+void asmlinkage car_stage_entry(void)
+{
+	verstage();
+}